To maintain a longer battery life, especially for handheld and biomedical SoC devices, it becomes important to reduce total charge drained, which is a combination of charge drained during both active cycle and standby (sleep) modes. Active cycle operations typically require supplying power to all functional (logic and memory) circuitry of the SoC device, and as such charge drain reduction schemes that can be implemented during active cycle operations is typically limited. Accordingly, the conventional methodology for reducing total charge drained typically involves switching the SoC device to a standby (sleep) mode (i.e., during inactive periods), which involves utilizing power switches to de-couple non-essential circuitry from the power supply.
SoC devices typically include a central processor and other logic circuitry, and one or more memory circuits. In order for the SoC device to switch quickly back from the standby mode to the active cycle mode quickly, power is maintained in critical areas, such as in the portion of the central processor that controls to power switches to “wake up” the powered-down circuitry, and memory circuits that store ongoing operating information. Because the memory circuits constitute a major part (typically up to 70%) of the silicon area for the current day SoC device, the power consumed by the memory circuits, even during standby mode, is significant. Further, as transistor device sizes continue to decrease (e.g., 0.13 microns or smaller), several issues begin to emerge with respect to the operation of SRAM cells, chiefly because at such dimensions the devices suffer from high values of leakage in the off state in standby mode. Essentially, these devices are no longer ideal switches; rather they are closer to sieves, having a non-negligible constant current flow path from drain to source or from drain/source to substrate even in the off state. The high leakage causes two major problems. First, because of the generation of large static current as leakage, there is increased static power consumption as a result. Second, which is more serious, is the issue of incorrect data reads from the SRAM cells. The accumulated leakage current from all the cells in a selected column is now comparable to the read current, thereby significantly eroding the bitline differential required for reliable sensing operations.
FIG. 11 is a simplified block diagram showing a simplified conventional memory circuit 50 utilized in a typical SoC device. Memory circuit 50 can be functionally divided into two regions: a memory cell array region 51 and a memory logic device region 52. Memory array region 51 includes SRAM memory cells that are typically sectioned into multiple sectors (e.g., sectors 52A and 52B), where the SRAM cells in each sector are arranged in rows and columns. Memory logic device region 52 is made up of logic circuitry that controls the memory read/write operations, and generally includes a memory controller 53, a row (X) decoder 54, a column (Y) decoder 55, row post-decoder and wordline driver circuits 56A and 56B, and sense amplifier and I/O circuitry 57. Memory controller 53 functions to receive read/write command signals R/W, data signals DATA, and optional address signals ADDR and a global clock signal from the SoC central processor (not shown), transmits corresponding row address signals X-ADDR to row decoder 54, transmits corresponding column address signals Y-ADDR to column decoder 56, generates other memory control signals CNTRL and a self-timing clock signal CLK_ST that are utilized to coordinate the read/write operation. Row decoder 54 partially decodes row address signal X-ADDR and transmits the partially decoded address data to post decoder circuitry that then controls (drives) associated wordlines in circuits 56A and 56B. Similarly, column decoder 55 decodes column address signal Y-ADDR to control sense amplifier and I/O circuitry 57.
In operation, at least a portion of memory controller 53 remains active during standby mode to receive address and data information from the SoC central processor (not shown). Upon receiving a read/write operation command signal R/W, memory controller 53 initiates (generates) self-timing clock signal CLK_ST and control signals CNTRL that prepare the remaining logic circuitry for the specified read/write operation. Prior to reading the single data bit stored on a targeted SRAM cell in a typical read operation, the bitlines connected to the targeted SRAM cell are precharged and equalized to a common value, and then the wordline connected to the targeted SRAM cell is activated by an associated wordline driver in one of circuits 56A or 56B such that the SRAM cell pulls one of the bitlines toward ground, with the other bitline remaining at the precharged level, typically VDD. That is, a first of the two bitlines is pulled low and the second bitline remains high when the stored data bit value is “0”, and the second bitline is pulled low and the first bitline remains high when the stored data bit value is “1”. The sense amplifier in circuit 57 senses the difference between the two bitlines once it exceeds a predetermined value, and the sensed difference is latched and output as the stored “0” or “1” data value.
As discussed above, the conventional method for maximizing battery life in portable SoC devices is to power-down non-critical portions of the logic circuitry of memory circuit 50 during standby modes. However, because SRAM cells require continuous power to retain stored data, and because the memory array 52 is required to store data even when memory circuit 50 is in the standby mode, power is consumed by the SRAM cells at all times. Further, because SRAM cells are produced using increasingly smaller transistors that exhibit higher current leakage, the leakage problem associated with SRAM arrays is becoming an increasingly significant problem.
Two prior are methods that attempt to address array leakage problem are described in U.S. Pat. Nos. 7,061,794 and 7,940,550. The method taught in U.S. Pat. No. 7,061,794 involves source biasing based on wordline selection. Specifically, a source-bias voltage is selectively applied to unselected SRAM cells based the currently selected wordline, where the source-bias voltage reduces source/drain leakage by reducing the source/drain voltage (i.e., by increasing the applied source voltage). However, the wordline source-bias approach has a disadvantage in that the associated logic circuitry has a significant area overhead (i.e., a significant portion of the SoC chip is needed to implement the wordline source-biasing circuitry). As indicated in FIG. 11, a second source biasing approach taught in U.S. Pat. No. 7,940,550 involves dividing memory array 52 into sectors 52A and 52B, and utilizing a source bias signal generator circuit 58 and source biasing circuits 59A and 59B to apply the source-bias voltage to the SRAM cells in non-selected memory sectors 52A or 52B based on the row address values generated by row decoder 54. Although this second approach reduces area overhead and provides some advantages over the wordline source-biasing approach, it still requires significant chip area to implement source-bias signal generator 58 and requires area between memory sectors 52A and 52B to implement source bias circuits 59A and 59B, and essentially only operates when the memory array sector is in a standby mode.
What is needed are improved systems and methods for reducing leakage in memory circuits in general, and in SRAM arrays in particular, that have minimal area overhead, and preferably function in both active cycle and standby modes.